By Patrick J. Quinn, Arthur H.M. van Roermund
This e-book proposes replacement switched capacitor suggestions which permit the success of upper intrinsic analogue useful accuracy than formerly attainable in such program components as analogue filter out and ADC layout. The validity of the ideas constructed and analyzed in Switched-Capacitor recommendations for High-Accuracy clear out and ADC layout has been proven in perform with the layout of CMOS SC bandpass filters and algorithmic ADC levels.
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Extra info for Switched-Capacitor Techniques for High-Accuracy Filter and ADC Design (Analog Circuits and Signal Processing)
Coutpar results from the junction capacitances at the drain nodes of all the output devices, as well as their gatedrain overlap capacitances. 5 and 2 depending on OTA topology and required output signal range. Other parasitic capacitances, in particular wiring capacitance, can be lumped together with the external load CL, or with the input capacitor Cin, for the sake of calculating the settling response. 26) +C in + 23 ◊ m ◊ C ox ◊ W ◊ L ˘˚ . Note that the amplifier transconductance gm and input capacitance Cinpar are related via the transition frequency w T (frequency of unity current gain) of the input devices by: g m = w T ◊ Cinpar .
M P7 ,M P8 can be say 4 times smaller than M P5 ,M P6 , with a corresponding increase in their Von voltage by a factor of 2. Typically, for a PMOS input stage as shown, the drain-bulk junction capacitance can be larger than the gate- ( ( ) ( ) ) VDD Vrefp 1 MP1 MP2 Vtail p Vrefp 2 MP4 MP5 Vout n MP9 MP3 MP6 Vin p Vref p3 Vin n MP7 MP8 MN7 MN8 Vrefn 2 MN 3 MN4 Vrefn 1 V SS MN 1 MN 5 MN6 MN2 Fig. 3 Fully differential current mirror OTA. 1. Review of Amplifier Architectures 41 ( ) source capacitance of each of the NMOS mirror transistors M N 5 ,M N 6 .
Note that the noise of the switches usually dominates the noise of the OTA since the OTA’s own noise is largely bandlimited by its own closed-loop bandwidth before it folds back. From the foregoing discussion, it is imperative to increase the signal range of the FD SC circuit by a factor of 2 compared to the equivalent SE SC circuit for optimum signal processing. The net result is at least a 3dB better SNR for a 3dB extra total power dissipation. For HF applications, the extra dissipation in the clock drivers is also important to the total power budget - the power dissipated by these drivers is doubled due to the doubling of the switch capacitance and the accompanying wiring capacitance.
Switched-Capacitor Techniques for High-Accuracy Filter and ADC Design (Analog Circuits and Signal Processing) by Patrick J. Quinn, Arthur H.M. van Roermund