By Rajesh Garg

ISBN-10: 1441909303

ISBN-13: 9781441909305

This booklet is prompted via the demanding situations confronted in designing trustworthy integratedsystems utilizing smooth VLSI methods. The trustworthy operation of built-in Circuits (ICs) has turn into more and more tough to accomplish within the deep sub-micron (DSM) period. With regularly lowering machine function sizes, mixed with decrease offer voltages and better working frequencies, the noise immunity of VLSI circuits is reducing alarmingly. therefore, VLSI circuits have gotten extra prone to noise results resembling crosstalk, energy provide adaptations and radiation-induced smooth errors.

This e-book describes the layout of resilient VLSI circuits. It provides algorithms to investigate the damaging results of radiation particle moves and processing adaptations at the electric habit of VLSI circuits, in addition to circuit layout thoughts to mitigate the effect of those problems.

  • Describes the cutting-edge within the components of radiation tolerant circuit layout and approach version tolerant circuit design;
  • Presents analytical techniques to check successfully the severity of electric results of radiation/process diversifications, in addition to options to lessen the results as a result of those problems;
  • Distills content material orientated towards nuclear engineers into modern algorithms and methods that may be understood simply and utilized by way of VLSI designers.

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Additional info for Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations

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Li, and S. P. Khatri, “Modeling dynamic stability of SRAMs in the presence of single event upsets (SEUs),” in Proc. of the Intl. Symposium on Circuits and Systems, May 2008, pp. 1788–1791. 35. R. Garg, N. Jayakumar, S. P. Khatri, and G. Choi, “A design approach for radiation-hard digital electronics,” in Proc. , July 2006, pp. 773–778. 36. R. Garg and S. P Khatri, “A novel, highly SEU tolerant digital circuit design approach,” in Proc. of the Intl. Conf. on Computer Design, Oct. 2008, pp. 14–20.

The case that is applicable). The derivation of the expression for t2 , for the different cases is as follows: Case 1. Consider the voltage and current waveforms of the 1 inverter during the radiation event as shown in Fig. 3. 3 shows the voltage of node a, IDS currents of M1 and M2, and the radiation-induced current pulse (iseu). As shown in Fig. t/ becomes equal to the IDS of M1, then at that instant, the IDS of M2 is approximately equal to 0 and the voltage at node a is VDD C jVTP j. This is an important observation because this information will be used as the initial condition Fig.

This is done to keep the analysis simple. It was found that neglecting the contribution of M2’s current minimally affect the accuracy of the proposed model. The value of VGM determines the case which is applicable. If Case 4 applies, then the pulse width is 0 since the radiation event does not affect the logic level of INV1. Otherwise, the times t1 and t2 are computed to calculate the pulse width of the voltage glitch at node a. 2 Derivation of the Expression for t1 As shown in the flowchart of the proposed model in Fig.

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Analysis and Design of Resilient VLSI Circuits: Mitigating Soft Errors and Process Variations by Rajesh Garg

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